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ISL12058
Low Cost and Low Power I2C-BusTM Real Time Clock/Calendar
Data Sheet June 15, 2009 FN6756.0
Low Power and Low Cost RTC with Alarm Function
The ISL12058 device is a low power real time clock with clock/calendar, and alarm function. The oscillator uses an external, low-cost 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction.
Features
* Real Time Clock/Calendar - Tracks Time in Hours, Minutes, and Seconds - Day of the Week, Date, Month, and Year * 4 Selectable Frequency Outputs * 2 Alarms - Settable to the Second, Minute, Hour, Day of the Week, Date, or Month * I2C Interface - 400kHz Data Transfer Rate * Small Package Options - 8 Ld 2mmx2mm TDFN Package - 8 Ld 3mmx3mm TDFN Package - 8 Ld MSOP Package - 8 Ld SOIC Package - Pb-Free (RoHS Compliant) * Low Cost 3V Alternative to ISL1208 and ISL12082
Pinouts
ISL12058 (8 LD SOIC, MSOP) TOP VIEW
X1 X2 NC GND 1 2 3 4 8 7 6 5 VDD IRQ/FOUT SCL SDA
Applications
* Utility Meters * HVAC Equipment * Audio/Video Components
ISL12058 (8 LD 2x2 TDFN, 8 LD 3x3 TDFN) TOP VIEW
X1 X2 NC GND 8 VDD 7 IRQ/FOUT 6 SCL 5 SDA
* Set-Top Box/Television * Modems * Network Routers, Hubs, Switches, Bridges
1 2 3 4
* Cellular Infrastructure Equipment * Fixed Broadband Wireless Equipment * Pagers/PDA * Point Of Sale Equipment * Test Meters/Fixtures * Office Automation (Copiers, Fax) * Home Appliances * Computer Products * Other Industrial/Medical/Automotive
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved I2C-busTM All other trademarks mentioned are the property of their respective owners.
ISL12058
.
Ordering Information
PART NUMBER ISL12058IBZ (Note 1) PART MARKING 12058 IBZ VDD RANGE (V) 1.4 to 3.6 1.4 to 3.6 1.4 to 3.6 1.4 to 3.6 1.4 to 3.6 1.4 to 3.6 1.4 to 3.6 TEMP. RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE (Pb-Free) 8 Ld SOIC 8 Ld SOIC (Tape and Reel) 8 Ld MSOP 8 Ld MSOP (Tape and Reel) 8 Ld TDFN 8 Ld TDFN (Tape and Reel) 8 Ld TDFN (Tape and Reel) PKG. DWG. # M8.15 M8.15 M8.118 M8.118 L8.3x3I L8.3x3I L8.2x2
ISL12058IBZ-T* (Note 1) 12058 IBZ ISL12058IUZ (Note 1) 12058
ISL12058IUZ-T* (Note 1) 12058 ISL12058IRTZ (Note 1) 2058
ISL12058IRTZ-T* (Note 1) 2058 ISL12058IRUZ-T* (Note 2) 058
*Please refer to TB347 for details on reel specifications. NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Block Diagram
SDA SCL SDA BUFFER SCL BUFFER SECONDS I2C INTERFACE RTC CONTROL LOGIC MINUTES HOURS DAY OF WEEK X1 X2 VDD CRYSTAL OSCILLATOR RTC DIVIDER DATE MONTH POR YEAR FREQUENCY OUT ALARM1 ALARM2 CONTROL REGISTERS
INTERNAL SUPPLY
IRQ/FOUT
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ISL12058 Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 SYMBOL X1 X2 NC GND SDA SCL IRQ/FOUT DESCRIPTION The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. No Connection. Can be connected to GND or left floating. Ground Serial Data (SDA) is a bi-directional pin used to transfer serial data into and out of the device. It has an open drain output and may be wire OR'ed with other open drain or open collector outputs. The Serial Clock (SCL) input is used to clock all serial data into and out of the device. Interrupt Output /Frequency Output is a multi-functional pin that can be used as alarm interrupt or frequency output pin. The function is set via the configuration register. This pin is open drain and requires an external pull-up resistor. It has a default output of 32.768kHz at power-up. Power supply
8
VDD
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Absolute Maximum Ratings
Voltage on VDD Pin (respect to GND) . . . . . . . . . . . . . . . -0.2V to 4V Voltage on IRQ/FOUT , SCL and SDA Pins (respect to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to 6V Voltage on X1 and X2 Pins (respect to GND) . . . . . . . . . -0.2V to 4V ESD Rating ((Per MIL-STD-883 Method 3014) Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>4kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>350V
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 8 Lead SOIC (Note 3) . . . . . . . . . . . . . 120 N/A 8 Lead MSOP (Note 3). . . . . . . . . . . . . 169 N/A 8 Lead TDFN (Note 3) . . . . . . . . . . . . 160 N/A 8 Lead TDFN (Notes 4, 5) . . . . . . . . . . 52 7 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
DC Operating Characteristics - RTC Temperature = -40C to +85C unless otherwise stated.
SYMBOL VDD VDDT IDD1 PARAMETER Main Power Supply Timekeeping Power Supply Standby Supply Current VDD = 3.6V VDD = 3.0V IDD2 Timekeeping Current VDD = 1.8V VDD = 1.4V IDD3 ILI ILO IRQ/FOUT VOL Output Low Voltage VDD = 1.8V, IOL = 3mA 0.4 V Supply Current With I2C Active at Clock Speed of 400kHz Input Leakage Current on SCL I/O Leakage Current on SDA -100 -100 100 100 nA nA VDD = 3.6V CONDITIONS MIN (Note 8) 1.8 1.4 600 500 400 350 15 40 650 TYP (Note 7) MAX (Note 8) 3.6 1.8 950 UNITS V V nA nA nA nA A 6 6, 12 6, 12 NOTES
Serial Interface Specifications
SYMBOL PARAMETER
Over the recommended operating conditions unless otherwise specified. TEST CONDITIONS MIN (Note 8) TYP (Note 7) MAX (Note 8) UNITS NOTES
SERIAL INTERFACE SPECS VIL VIH SDA and SCL Input Buffer LOW Voltage SDA and SCL Input Buffer HIGH Voltage -0.3 0.7 x VDD 0.04 x VDD VDD + 2 VDD > 1.8V, VPULLUP = 5.0V TA = +25C, f = 1MHz, VDD = 5V, VIN = 0V, VOUT = 0V 0 0.4 10 400 0.3 x VDD 5.5 V V V V V pF kHz 9, 10 11
Hysteresis SDA and SCL Input Buffer Hysteresis VPULLUP VOL Cpin fSCL Maximum Pull-up Voltage on SDA during I2C Communication SDA Output Buffer LOW Voltage, Sinking 3mA SDA and SCL Pin Capacitance SCL Frequency
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Serial Interface Specifications
SYMBOL tIN tAA PARAMETER Pulse width Suppression Time at SDA and SCL Inputs SCL Falling Edge to SDA Output Data Valid Over the recommended operating conditions unless otherwise specified. (Continued) TEST CONDITIONS Any pulse narrower than the max spec is suppressed SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of VDD window 1300 MIN (Note 8) TYP (Note 7) MAX (Note 8) 50 900 UNITS NOTES ns ns 11
tBUF
Time the Bus Must be Free Before SDA crossing 70% of VDD during a the Start of a New Transmission STOP condition, to SDA crossing 70% of VDD during the following START condition Clock LOW Time Clock HIGH Time START Condition Setup Time START Condition Hold Time Measured at the 30% of VDD crossing Measured at the 70% of VDD crossing SCL rising edge to SDA falling edge. Both crossing 70% of VDD From SDA falling edge crossing 30% of VDD to SCL falling edge crossing 70% of VDD From SDA exiting the 30% to 70% of VDD window, to SCL rising edge crossing 30% of VDD From SCL falling edge crossing 30% of VDD to SDA entering the 30% to 70% of VDD window From SCL rising edge crossing 70% of VDD, to SDA rising edge crossing 30% of VDD From SDA rising edge to SCL falling edge. Both crossing 70% of VDD From SCL falling edge crossing 30% of VDD, until SDA enters the 30% to 70% of VDD window From 30% to 70% of VDD From 70% to 30% of VDD
ns
tLOW tHIGH tSU:STA tHD:STA
1300 600 600 600
ns ns ns ns
tSU:DAT
Input Data Setup Time
100
ns
tHD:DAT
Input Data Hold Time
0
900
ns
tSU:STO
STOP Condition Setup Time
600
ns
tHD:STO
STOP Condition Hold Time
600
ns
tDH
Output Data Hold Time
0
ns
tR tF Cb Rpu
SDA and SCL Rise Time SDA and SCL Fall Time
20 + 0.1 x Cb 20 + 0.1 x Cb 10 1
300 300 400
ns ns pF k
9, 10 9, 10, 11 9, 10 9, 10
Capacitive Loading of SDA or SCL Total on-chip and off-chip SDA and SCL Bus Pull-Up Resistor Off-Chip Maximum is determined by tR and tF. For Cb = 400pF, max is about 2k to~2.5k. For Cb = 40pF, max is about 15k to ~20k
NOTES: 6. IRQ/FOUT inactive. 7. Typical values are for T = +25C and 3.3V supply voltage. 8. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 9. Limits should be considered typical and are not production tested. 10. These are I2C specific parameters and are not production tested, however, they are used to set conditions for testing devices to validate specification. 11. Parts will work with SDA pull-up voltage above the VPULLUP limit but the tAA and tFin the I2C parameters are not guaranteed. 12. Specified at +25C.
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ISL12058 SDA vs SCL Timing
tF tHIGH tLOW tR
SCL tSU:STA tHD:STA SDA (INPUT TIMING)
tSU:DAT tHD:DAT tSU:STO
tAA SDA (OUTPUT TIMING)
tDH
tBUF
Symbol Table
WAVEFORM INPUTS Must be steady OUTPUTS Will be steady
May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A
Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 3.0V 5.0V 1533 SDA, IRQ/FOUT 100pF FOR VOL= 0.4V AND IOL = 3mA
FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING THE DEVICE WITH VDD = 3.0V, VPULLUP = 5.0V
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ISL12058 Typical Performance Curves
0.7 0.6 0.5 IDD1 (A) 0.4 0.3 0.2 0.1 0 1.4 1.9 2.4 VDD (V) 2.9 3.4 0.2 -40 IDD1 (A) 0.8 3.6 0.6 3.0 0.4 1.8 1.4 -20 0 20 40 60 80
Temperature is +25C unless otherwise specified
1.0
TEMPERATURE (C)
FIGURE 2. IDD1 vs VDD
FIGURE 3. IDD1 vs TEMPERATURE
1.2 1.1 1.0 0.9 8192Hz 4096Hz FOUT (Hz) 1Hz 1.9 2.4 VDD (V) 2.9 3.4 IDD (A) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 1.4 32768Hz
32769.0 32768.8 32768.6 32768.4 32768.2 32768.0 32767.8 32767.6 32767.4 32767.2 32767.0 1.4 1.9 2.4 VDD (V) 2.9 3.4
FIGURE 4. IDD vs VDD vs FOUT
FIGURE 5. FOUT vs VDD WITH A TYPICAL 32.768kHZ CRYSTAL
General Description
The ISL12058 device is a low power real time clock with clock/calendar, and alarm. The oscillator uses an external, low-cost 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction. The ISL12058's flexible alarm can be set to any clock/calendar value for a match. For example, every minute, every Tuesday or at 5:23 AM on March 21. The alarm status is available by checking the Status Register, or the device can be configured to provide a hardware interrupt via the IRQ/FOUT pin.
Pin Descriptions
X1, X2
The X1 and X2 pins are the input and output, respectively, of an inverting amplifier. An external 32.768kHz quartz crystal is used with the ISL12058 to supply a timebase for the real time clock. Refer to Figure 6. The device can also be driven directly from a 32.768kHz square wave source with peak to peak voltage from 0V to VDD at X1 pin with X2 pin floating.
X1 X2
FIGURE 6. RECOMMENDED CRYSTAL CONNECTION
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ISL12058
IRQ/FOUT (Interrupt Output/Frequency Output)
This dual function pin can be used as an interrupt or frequency output pin. The IRQ/FOUT mode is selected via the IRQE bit of the control register (address 08h). The IRQ/FOUT is an open drain output and requires the use of a pull-up resistor, and it can accept a pull-up voltage up to 5.5V. This pin has a default output of 32.768kHz at power-up. * Interrupt Mode. The pin provides an interrupt signal output. This signal notifies a host processor that an alarm has occurred and requests action. * Frequency Output Mode. The pin outputs a clock signal which is related to the crystal frequency. The frequency output is user selectable and enabled via the I2C bus.
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the frequency of the quartz crystal that is used as the time base for the RTC. Since the resonant frequency of a crystal is temperature dependent, the RTC performance will also be dependent upon temperature. The frequency deviation of the crystal is a function of the turnover temperature of the crystal from the crystal's nominal frequency. For example, a ~20ppm frequency deviation translates into an accuracy of ~1 minute per month. These parameters are available from the crystal manufacturer.
Alarm Interrupt
The alarm interrupt mode is enabled by setting IRQE bit to `1' with Alarm1 enables by setting ALM1E to `1'. The standard alarm allows for alarms of time, date, day of the week, month, and year. When a time alarm occurs, the IRQ/FOUT pin will be pulled low and the alarm interrupt bit (A1F) will be set to "1".
NOTE: The A1F bit can be reset by the user or cleared automatically using the Auto Reset mode (see ARST bit, address 07h). Alarm2 does not have hardware interrupt function.
Serial Clock (SCL)
The SCL input is used to clock all serial data into and out of the device. The input buffer on this pin is always active (not gated). The SCL pin can accept a logic high voltage up to 5.5V.
Serial Data (SDA)
SDA is a bi-directional pin used to transfer data into and out of the device. It has an open drain output and may be ORed with other open drain or open collector outputs. The input buffer is always active (not gated) in normal mode. An open drain output requires the use of a pull-up resistor, and it can accept a pull-up voltage up to 5.5V. The output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down. The circuit is designed for 400kHz I2C interface speeds.
NOTE: Parts will work with SDA pull-up voltage above the VPULLUP limit but the tAA and tFin the I2C parameters are not guaranteed.
Frequency Output Mode
The ISL12058 has the option to provide a frequency output signal using the IRQ/FOUT pin. The frequency output mode is set by using the FO bits to select 4 possible output frequency values from 1Hz to 32.768kHz. The IRQE bit must be set to `0' for frequency output.
I2C Serial Interface
The ISL12058 has an I2C serial bus interface that provides access to the real time clock registers, control and status registers and the alarm registers. The I2C serial interface is compatible with other industry I2C serial bus protocols using a bi-directional data signal (SDA) and a clock signal (SCL).
VDD, GND
Chip power supply and ground pins. The device will have full operation with a power supply from 1.8V to 3.6V, and timekeeping function with a power supply from 1.4V to 3.6V. A 0.1F decoupling capacitor is recommended on the VDD pin to ground.
Register Descriptions
The registers are accessible following a slave byte of "1101111x" and reads or writes to addresses [00h:1Fh]. The defined addresses and default values are described in Table 1. Address 15h to 1Fh are not used. Reads or writes to 15h to 1Fh will not affect operation of the device but should be avoided. For Page Write and Page Read operation, the address will wrap around from address 1Fh to 00h. REGISTER ACCESS The contents of the registers can be modified by performing a byte or a page write operation directly to any register address. The registers are divided into 3 sections. These are: 1. Real Time Clock (7 bytes): Address 00h to 06h. 2. Control and Status (2 bytes): Address 07h to 08h. 3. Alarm1 and Alarm2 (9 bytes): Address 0Ch to 14h. There are no addresses above 1Fh.
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NC (No Connection)
The NC pin is not connected to the die. The pin can be connected to GND or left floating.
Functional Description
Real Time Clock Operation
The Real Time Clock (RTC) uses an external 32.768kHz quartz crystal to maintain an accurate internal representation of second, minute, hour, day of week, date, month, and year. The RTC also has leap-year correction. The RTC also corrects for months having fewer than 31 days and has a bit that controls 24 hour or AM/PM format. When the ISL12058 powers up after the loss of VDD, the clock will not begin incrementing until at least one byte is written to the clock register. 8
ISL12058
TABLE 1. REGISTER MEMORY MAP REG NAME SC MN HR RTC DT MO YR DW Status Control SR INT Not Used Not Used Not Used A1SC A1MN A1HR Alarm1 0Fh 10h 11h 12h 13h Alarm2 14h A2DW/DT A2M4 A2DW/DT A2DT21 A2DT20 A2DT13 A2DT12 A2DW12 A2DT11 A2DW11 A2DT10 A2DW10 1 to 31 0 to 6 00h 00h A1DT A1MO A1DW A2MN A2HR A1M4 A1M5 A1M6 A2M2 A2M3 0 0 0 A2MN22 A2MIL A1DT21 0 0 A2MN21 A2HR21 A1DT20 A1MO20 0 A2MN20 A2HR20 A1DT13 A1MO13 0 A2MN13 A2HR13 A1DT12 A1MO12 A1DW12 A2MN12 A2HR12 A1DT11 A1MO11 A1DW11 A2MN11 A2HR11 A1DT10 A1MO10 A1DW10 A2MN10 A2HR10 1 to 31 1 to 12 0 to 6 00 to 59 0 to 23 00h 00h 00h 00h 00h BIT 7 0 0 MIL 0 0 YR23 0 ARST 0 0 0 0 A1M1 A1M2 A1M3 6 SC22 MN22 0 0 0 YR22 0 XSTOP ALM1E 0 0 0 A1SC22 A1MN22 A1MIL 5 SC21 MN21 HR21 DT21 0 YR21 0 0 ALM2E 0 0 0 A1SC21 A1MN21 A1HR21 4 SC20 MN20 HR20 DT20 MO20 YR20 0 WRTC FO1 0 0 0 A1SC20 A1MN20 A1HR20 3 SC13 MN13 HR13 DT13 MO13 YR13 0 OSF FO0 0 0 0 A1SC13 A1MN13 A1HR13 2 SC12 MN12 HR12 DT12 MO12 YR12 DW12 A1F IRQE 0 0 0 A1SC12 A1MN12 A1HR12 1 SC11 MN11 HR11 DT11 MO11 YR11 DW11 A2F 0 0 0 0 A1SC11 A1MN11 A1HR11 0 SC10 MN10 HR10 DT10 MO10 YR10 DW10 PF A1E 0 0 0 A1SC10 A1MN10 A1HR10 REG RANGE DEFAULT 0 to 59 0 to 59 0 to 23 1 to 31 1 to 12 0 to 99 0 to 6 N/A N/A N/A N/A N/A 00 to 59 00 to 59 0 to 23 00h 00h 00h 01h 01h 00h 00h 09h 18h 00h 00h 00h 00h 00h 00h
ADDR. SECTION 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh
Address 09h to 0Bh and 15h to 1Fh are not used. Reads or writes to these registers will not affect operation of the device but should be avoided. A register can be read by performing a random read at any address at any time. This returns the contents of that register location. Additional registers are read by performing a sequential read. For the RTC registers, the read instruction latches all clock registers into a buffer, so an update of the clock does not change the time being read. A sequential read will not result in the output of data from the memory array. At the end of a read, the master supplies a stop condition to end the operation and free the bus. After a read or write instruction, the address remains at the previous address +1 so the user can execute a current address read and continue reading the next register.
.
Real Time Clock Registers
Addresses [00h to 06h]
RTC REGISTERS (SC, MN, HR,DW, DT, MO, YR) These registers depict BCD representations of the time. As such, SC (Seconds, address 00h) and MN (Minutes, address 01h) range from 0 to 59, HR (Hour, address 02h) can either be a 12-hour or 24-hour mode, DT (Date, address 03h) is 1 to 31, MO (Month, address 04h) is 1 to 12, YR (Year, address 06h) is 0 to 99, and DW (Day of the Week, address 06h) is 0 to 6. The DW register provides a Day of the Week status and uses three bits DW2 to DW0 to represent the seven days of the week. The counter advances in the cycle 0-1-2-3-4-5-6-0-12-... The assignment of a numerical value to a specific day of the week is arbitrary and may be decided by the system software designer. The default value is defined as "0".
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24 HOUR TIME If the MIL bit of the HR register is "1", the RTC uses a 24-hour format. If the MIL bit is "0", the RTC uses a 12-hour format and HR21 bit functions as an AM/PM indicator with a "1" representing PM. The clock defaults to 12-hour format time with HR21 = "0". If the A1HR and/or A2HR registers are used for alarm interrupt, the A1HR and/or A2HR registers must set to the same hour format as the HR register. For example, if the HR register is set to 24-hour format by setting the MIL bit to "1", then the AxHR register must be set to 24-hour format with AxMIL bit set to "1". If the hour format does not match between the HR register and the AxHR register, then the alarm interrupt will not trigger. LEAP YEARS Leap years add the day February 29 and are defined as those years that are divisible by 4. Years divisible by 100 are not leap years, unless they are also divisible by 400. This means that the year 2000 is a leap year, the year 2100 is not. The ISL12058 does not correct for the leap year in the year 2100. ALARM2 INTERRUPT BIT (A2F) These bits announce if the Alarm2 matches the real time clock. If there is a match, the respective bit is set to "1". This bit is manually reset to "0" by the user. A write to this bit in the SR can only set it to "0", not "1". OSCILLATOR FAIL BIT (OSF) Oscillator Fail Indicator bit (OSF). This bit is set to a "1" when there is no oscillation on X1 pin. The OSF bit can only be reset by having an oscillation on X1 and manually reset to "0" to reset it. WRITE RTC ENABLE BIT (WRTC) The WRTC bit enables or disables write capability into the RTC Timing Registers. The factory default setting of this bit is "0". Upon initialization or power-up, the WRTC must be set to "1" to enable the RTC. Upon the completion of a valid write (STOP), the RTC starts counting. The RTC internal 1Hz signal is synchronized to the STOP condition during a valid write cycle. CRYSTAL OSCILLATOR ENABLE BIT (XSTOP) This bit enables/disables the internal crystal oscillator. When the XSTOP is set to "1", the oscillator is disabled. The XSTOP bit is set to "0" on power-up for normal operation. AUTO RESET ENABLE BIT (ARST) This bit enables/disables the automatic reset of the A1F and A2F status bits only. When ARST bit is set to "1", these status bits are reset to "0" after a valid read of the respective status register (with a valid STOP condition). When the ARST is cleared to "0", the user must manually reset the A1F and A2F bits.
Control and Status Registers
Addresses [07h to 0Bh]
The Control and Status Registers consist of the Status Register, Interrupt Register, and Alarm Registers.
Status Register (SR) [Address 07h]
The Status Register is located in the memory map at address 0Bh. This is a volatile register that provides either control or status of alarm interrupt and crystal oscillator enable. Refer to Table 2.
TABLE 2. STATUS REGISTER (SR) ADDR 07h Default 7 ARST 0 6 XSTOP 0 5 0 0 4 3 2 1 0 PF
Interrupt Control Register (INT) [Address 08h]
TABLE 3. INTERRUPT CONTROL REGISTER (INT) ADDR 7 0 0 6 ALM1E 0 5 ALM2E 0 4 3 2 1 0 0 0 A1E 0
WRTC OSF A1F A2F 0 1 0 0
08h 1 Default
FO1 FO0 IRQE 1 1 0
NOTE: read operation will remain set after the read operation is complete.
ALARM1 INTERRUPT ENABLE BIT (A1E) This bit enables the hardware interrupt function of ALARM1 to IRQ/FOUT pin. When A1E set to `1', IRQE set to `1' and ALM1E set to `1', the IRQ/FOUT pin will pull low when the A1F bit is set by the ALARM1 interrupt. IRQ/FOUT FUNCTION SELECTION BIT (IRQE) This bit selects the function of the IRQ/FOUT pin. Refer to Table 4 for function selection of IRQ/FOUT PIN.
TABLE 4. FUNCTION SELECTION OF IRQ/FOUT PIN WITH A1E AND IRQE BITS A1E 0 0 IRQE 0 1 IRQ/FOUT FUNCTION FOUT High Impedance
POWER FAILURE BIT (PF) This bit is set to a "1" after a total power failure. This is a read only bit that is set by hardware (ISL12058 internally) when the device powers up after having lost power to the device. On power-up after a total power failure, all registers are set to their default states. The first valid write to the RTC section after a complete power failure resets the PF bit to "0" (writing one RTC register is sufficient). ALARM1 INTERRUPT BIT (A1F) These bits announce if the Alarm1 matches the real time clock. If there is a match, the respective bit is set to "1". This bit is manually reset to "0" by the user. A write to this bit in the SR can only set it to "0", not "1".
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ISL12058
TABLE 4. FUNCTION SELECTION OF IRQ/FOUT PIN WITH A1E AND IRQE BITS (Continued) A1E 1 1 IRQE 0 1 IRQ/FOUT FUNCTION FOUT Alarm 1 Interrupt TABLE 6. ALARM1 INTERRUPT WITH ENABLE BITS SELECTION A1M1 0 1 0 0 0 0 0 1 1 1 . . . 0 1 A1M2 0 0 1 0 0 0 0 1 0 1 . . . 0 0 A1M3 0 0 0 1 0 0 0 0 1 1 . . . 0 0 A1M4 0 0 0 0 1 0 0 0 0 0 . . . 1 1 A1M5 0 0 0 0 0 1 0 0 0 0 . . . 1 1 A1M6 0 0 0 0 0 0 1 0 0 0 . . . 1 1 Match Date, Month, and Day Match Second, Date, Month, and Day . . . Match MInute, Hour, Date, Month, and Day Match Second, MInute, Hour, Date, Month, and Day ALARM1 Interrupt Every Second Match Second Match Minute Match Hour Match Date Match Month Match Day Match Second and Minute Match Second and Hour Match Second, Minute, and Hour
FREQUENCY OUT CONTROL BITS (FO <1:0>) These bits select the output frequency at the IRQ/FOUT pin. IRQE must be set to "0" for frequency output at the IRQ/FOUT pin. Refer to Table 5 for frequency selection.
TABLE 5. FREQUENCY SELECTION OF IRQ/FOUT PIN WITH FO1 AND FO0 BITS FO1 1 1 0 0 FO0 1 0 1 0 FREQUENCY, FOUT (Hz) 32768 8192 4096 1 COMMENT Free running crystal clock Free running crystal clock Free running crystal clock Sync. at RTC write
ALARM ENABLE BITS (ALM1E, ALM2E) This bit enables/disables the Alarm1 and Alarm2 function. When the ALM1E bit is set to "1", the Alarm1 function is enabled. When the ALM1E is cleared to "0", the alarm function is disabled. ALM1E bit is set to "0" at power-up. When the ALM2E bit is set to "1", the Alarm2 function is enabled. When the ALM2E is cleared to "0", the alarm function is disabled. ALM2E bit is set to "0" at power-up.
NOTE: The Alarm1 has hardware function via the IRQ/FOUT pin. Alarm2 does not have hardware interrupt function.
. . . 0
. . 1
. . . 1
. . . 1
. . . 1
. . . 1
1
1
1
1
1
1
Alarm1 Registers
Addresses [Address 0Ch to 11h]
The Alarm1 register bytes are set up identical to the RTC register bytes, except that the MSB of each byte functions as an enable bit (enable = "1"). These enable bits specify which alarm registers (seconds, minutes, etc) are used to make the comparison. Note that there is no alarm byte for year. When all the enable bits are set to "0" with ALM1E set to "1", the Alarm 1 will triggered once a second. The Alarm1 function works as a comparison between the Alarm1 registers and the RTC registers. As the RTC advances, the Alarm1 will be triggered once a match occurs between the Alarm1 registers and the RTC registers. Any one Alarm1 register, multiple registers, or all registers can be enabled for a match. To clear an Alarm1, the A1F status bit can be set to "0" with a write or use the ARST bit auto reset function. Following is example of Alarm1 Interrupt.
Example - A single alarm will occur on January 1 at 11:30am. A. Set Alarm1 registers as follows:
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FN6756.0 June 15, 2009
ISL12058
ALARM1 REGISTER 7 A1SC A1MN A1HR A1DT A1MO A1DW 0 1 1 1 1 0 BIT 6 0 0 0 0 0 0 5 0 1 0 0 0 0 4 0 1 1 0 0 0 3 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 HEX DESCRIPTION A2DW/DT A2M2 0 0 0 0 1 0 0 0 0 1 1 0 0 1 HEX DESCRIPTION 1 1 1 0 1 0 0 0 1 1 0 1 1 1 0 1 A2M3 0 0 1 0 0 1 0 1 1 1 0 1 1 A2M4 0 0 0 1 1 0 1 1 1 0 1 1 1 ALARM2 Interrupt Every Minute (Second=00) Match Minute Match Hour Match Date Match Day Match Minute and Hour Match Minute and Date Match Hour and Date Match Minute, Hour, and Date Match Minute and Hour Match Minute and Day Match Hour and Day Match Minute, Hour, and Day TABLE 7. ALARM2 INTERRUPT WITH ENABLE BITS SELECTION 00h Seconds disabled B0h Minutes set to 30, enabled 91h Hours set to 11, enabled 81h Date set to 1, enabled 81h Month set to 1, enabled 00h Day of week disabled
B. Also the ALME bit must be set as follows:
CONTROL REGISTER 7 INT 0 BIT 6 1 5 x 4 x 3 x 2 1
45h Enable Alarm1, and Alarm1 Interrupt to IRQ/FOUT
xx indicate other control bits and these bit can be set to 0 or 1. After these registers are set, the Alarm1 interrupt will be generated when the RTC advances to exactly 11:30am on January 1 (after seconds changes from 59 to 00) by setting the A1F bit in the status register to "1" and also bringing the IRQ/FOUT output low.
Following is example of Alarm2 Interrupt. Example - A single alarm will occur on every Monday at 20:00 military time (Monday is when DW = 1). A. Set Alarm registers as follows:
ALARM2 REGISTER 7 A2MN 0 1 1 BIT 6 0 1 1 5 0 1 0 4 0 0 0 3 0 0 0 2 0 0 0 1 0 0 0 0 0 0 1 HEX DESCRIPTION
00h Minutes disabled E0h Hours set to 20, enabled C1h Day set to Monday, enabled
Alarm2 Registers
Addresses [Address 12h to 14h]
The Alarm2 register bytes are set up identical to the RTC register bytes except that the MSB of each byte functions as an enable bit (enable = "1"). These enable bits specify which alarm registers (minutes, hour, and date/day) are used to make the comparison. Note that there are no alarm bytes for second, month and year. When all the enable bits are set to "0" with ALM2E set to "1", the Alarm2 will triggered once a minute when second hits "00". The Alarm2 function works as a comparison between the Alarm2 registers and the RTC registers. As the RTC advances, the Alarm2 will be triggered once a match occurs between the Alarm2 registers and the RTC registers. Any one Alarm2 register, multiple registers, or all registers can be enabled for a match. To clear an Alarm2, the A2F status bit can be set to "0" with a write or use the ARST bit auto reset function.
A2HR A2DW/DT
After these registers are set, an alarm will be generated when the RTC advances to exactly 20:00 on Monday (after minutes changes from 59 to 00) by setting the A2F bit in the status register to "1".
I2C Serial Interface
The ISL12058 supports a bi-directional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is the master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL12058 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first.
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ISL12058
Protocol Conventions
Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 7). On power-up of the ISL12058, the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL12058 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 7). A START condition is ignored during the power-up sequence. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 7). A STOP condition at the end of a read operation or at the end of a write operation to memory only places the device in its standby mode. An acknowledge (ACK) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting 8 bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the 8 bits of data (see Figure 8). The ISL12058 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL12058 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation.
SCL
SDA
START
DATA STABLE
DATA CHANGE
DATA STABLE
STOP
FIGURE 7. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM MASTER
1
8
9
SDA OUTPUT FROM TRANSMITTER
HIGH IMPEDANCE
SDA OUTPUT FROM RECEIVER
HIGH IMPEDANCE
START
ACK
FIGURE 8. ACKNOWLEDGE RESPONSE FROM RECEIVER
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ISL12058
R/W BIT = "0" SIGNALS FROM THE MASTER S T A R T LAST DATA BYTE S T O P
IDENTIFICATION BYTE
ADDRESS BYTE
FIRST DATA BYTE
SIGNAL AT SDA SIGNALS FROM THE ISL12058
11011110 A C K A C K A C K A C K A C K
FIGURE 9. SEQUENTIAL BYTE WRITE SEQUENCE
Device Addressing
Following a start condition, the master must output a Slave Address Byte. The 7 MSBs of the Slave Address Byte are the device identifier bits, and the device identifier bits are "1101111". The last bit of the Slave Address Byte defines a read or write operation to be performed. When this R/W bit is a "1", then a read operation is selected. A "0" selects a write operation (refer to Figure 10). After loading the entire Slave Address Byte from the SDA bus, the ISL12058 compares the device identifier bits with "1101111". Upon a correct compare, the device outputs an acknowledge on the SDA line. Following the Slave Address Byte is a 1 byte register address. The register address is supplied by the master device. On power-up, the internal address counter is set to address 0h, so a current address read of the RTC array starts at address 0h. When required, as part of a random read, the master must supply the 1 Word Address Bytes as shown in Figure 11. In a random read operation, the slave byte in the "dummy write" portion must match the slave byte in the "read" section. For a random read of the Clock/Control Registers, the slave byte must be "1101111x" in both places.
1 1 0 1 1 1 1 R/W SLAVE ADDRESS BYTE
Write Operation
A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL12058 responds with an ACK. At this time, the I2C interface enters a standby state.
Read Operation
A Read operation consists of a three byte instruction followed by one or more Data Bytes (see Figure 11). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to "0", an Address Byte, a second START, and a second Identification byte with the R/W bit set to "1". After each of the three bytes, the ISL12058 responds with an ACK. Then the ISL12058 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The master terminates the read operation (issuing a STOP condition) following the last bit of the last Data Byte (see Figure 11). The Data Bytes are from the memory location indicated by an internal pointer. This pointer's initial value is determined by the Address Byte in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the memory location 1Fh, the pointer "rolls over" to 00h, and the device continues to output data for each ACK received.
A7
A6
A5
A4
A3
A2
A1
A0
REGISTER ADDRESS DATA BYTE
D7
D6
D5
D4
D3
D2
D1
D0
FIGURE 10. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES
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FN6756.0 June 15, 2009
ISL12058 Application Section
SIGNALS FROM THE MASTER S T A R T R/W BIT ="0" IDENTIFICATION BYTE WITH R/W = 0 ADDRESS BYTE S T IDENTIFICATION A BYTE WITH R R/W = 1 T R/W BIT = "1" A C K A C K S T O P
SIGNAL AT SDA SIGNALS FROM THE SLAVE
11011110 A C K A C K
11011111 A C K
FIRST READ DATA BYTE
LAST READ DATA BYTE
FIGURE 11. MULTIPLE BYTES READ SEQUENCE
Oscillator Crystal Requirements
The ISL12058 uses a standard 32.768kHz crystal. Either through hole or surface mount crystals can be used. Table 8 lists some recommended surface mount crystals and the parameters of each. This list is not exhaustive and other surface mount devices can be used with the ISL12058 if their specifications are very similar to the devices listed. The crystal should have a required parallel load capacitance of 12.5pF and an equivalent series resistance of less than 50k. The crystal's temperature range specification should match the application. Many crystals are rated for -10C to +60C (especially through-hole and tuning fork types), so an appropriate crystal should be selected if extended temperature range is required.
.
Figure 12 shows a suggested layout for the ISL12058 device using a surface mount crystal. Two main precautions should be followed: 1. Do not run the serial bus lines or any high speed logic lines in the vicinity of the crystal. These logic level lines can induce noise in the oscillator circuit to cause misclocking. 2. Add a ground trace around the crystal with one end terminated at the chip ground. This will provide termination for emitted noise in the vicinity of the RTC device. In addition, it is a good idea to avoid a ground plane under the X1 and X2 pins and the crystal, as this will affect the load capacitance and therefore the oscillator accuracy of the circuit. If the IRQ/FOUT pin is used as a clock, it should be routed away from the RTC device as well. The traces for the VDD pins can be treated as a ground, and should be routed around the crystal.
TABLE 8. SUGGESTED SURFACE MOUNT CRYSTALS MANUFACTURER Citizen MicroCrystal Raltron SaRonix Ecliptek ECS Fox PART NUMBER CM200S MS3V RSM-200S 32S12 ECPSM29T-32.768K ECX-306 FSM-327
Layout Considerations
The crystal input at X1 has a very high impedance, and oscillator circuits operating at low frequencies (such as 32.768kHz) are known to pick up noise very easily if layout precautions are not followed. Most instances of erratic clocking or large accuracy errors can be traced to the susceptibility of the oscillator circuit to interference from adjacent high speed clock or data lines. Careful layout of the RTC circuit will avoid noise pickup and insure accurate clocking.
FIGURE 12. SUGGESTED LAYOUT FOR ISL12058 AND
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FN6756.0 June 15, 2009
ISL12058 Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1 -BE
INCHES SYMBOL A
ABC
MILLIMETERS MIN 0.94 0.05 0.75 0.25 0.09 2.95 2.95 4.75 0.40 8 0.07 0.07 5o 0o 15o 6o MAX 1.10 0.15 0.95 0.36 0.20 3.05 3.05 5.05 0.70 NOTES 9 3 4 6 7 Rev. 2 01/03
MIN 0.037 0.002 0.030 0.010 0.004 0.116 0.116 0.187 0.016 8 0.003 0.003 5o 0o
MAX 0.043 0.006 0.037 0.014 0.008 0.120 0.120 0.199 0.028
INDEX AREA
12 TOP VIEW
0.20 (0.008)
A1 A2
4X
0.25 (0.010) GAUGE PLANE SEATING PLANE -C-
R1 R
b c D E1
A
A2
4X
L L1
e E L L1 N R
0.026 BSC
0.65 BSC
A1
-He D
b
0.10 (0.004) -A0.20 (0.008)
C
SEATING PLANE
0.037 REF
0.95 REF
C a C L E1
C
R1 0
SIDE VIEW
15o 6o
-B-
0.20 (0.008)
CD
END VIEW
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
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FN6756.0 June 15, 2009
ISL12058
Package Outline Drawing
L8.2x2
8 Lead Ultra Thin Dual Flat No-Lead COL Plastic Package (UTDFN COL) Rev 3, 11/07
2X 1.5 2.00 6 PIN 1 INDEX AREA A PIN #1 INDEX AREA 6 B 1 1X 0.5 0.1 6X 0.50 4 7X 0.4 0.1
2.00
(4X)
0.15 8
TOP VIEW BOTTOM VIEW
5
0.10 M C A B 4 0.25 +0.05 / -0.07
( 8X 0 . 25 ) SEE DETAIL "X" ( 1X 0 .70 ) 0 . 55 MAX
0.10 C
C
BASE PLANE
SEATING PLANE 0.08 C
(1.8 )
SIDE VIEW
( 7X 0 . 60 )
C
0 . 2 REF
0 . 00 MIN. 0 . 05 MAX. ( 6X 0 . 5 )
TYPICAL RECOMMENDED LAND PATTERN DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
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FN6756.0 June 15, 2009
ISL12058
Package Outline Drawing
L8.3x3I
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 1 6/09
2X 1.950 3.00 (4X) 0.15 A B 6X 0.65
5
8
3.00
1.64 +0.10/ - 0.15
6 PIN 1 INDEX AREA 8X 0.400 0.10
PIN #1 INDEX AREA
6
4
TOP VIEW
1
8X 0.30 0.10 M C A B 2.38 +0.10/ - 0.15 4
BOTTOM VIEW
SEE DETAIL "X" ( 2.38 ) ( 1.95)
0.10 C
Max 0.80
C
0.08 C
( 8X 0.60) (1.64) ( 2.80 )
SIDE VIEW
PIN 1 (6x 0.65) ( 8 X 0.30)
C
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. 4. Unless otherwise specified, tolerance : Decimal 0.05 Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
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FN6756.0 June 15, 2009
ISL12058 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45 H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 8 8 0 8 MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 0.2284 0.0099 0.016 8 0
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 0.2440 0.0196 0.050
B C D E e H
C
A1 0.10(0.004)
0.050 BSC
1.27 BSC
e
B 0.25(0.010) M C AM BS
h L N
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 19
FN6756.0 June 15, 2009

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